AMD CTO Mark Papermaster has confirmed the release window for the company’s next-gen CPU architecture, scheduled for July 22-23, 2026. For this initial rollout, the company will focus on its server and datacenter Epyc processor family, which will be optimised for traditional x86 enterprise workloads.
According to Papermaster, Zen 6 will be officially revealed at AMD’s Advancing AI event in San Francisco. Zen 6 will first appear inside the brand’s Epyc server CPUs powering Helios AI servers, offering higher core counts and memory channels than their Zen 5 equivalents, alongside next-gen connections and improved power efficiency. Papermaster says Zen 6 Epyc CPUs will continue to lead in x86 CPU performance.
“I’ll say for me, every enterprise conversation I’m having now, this comes up. Because enterprises have, you know, decades of running x86. They’re not going to move that install base,” said Papermaster in the announcement. “And what we’ve done at AMD, you know, since we launched the new Zen processor back in 2017. We’re now on our sixth generation. So, at our Advancing AI event on July 22nd and 23rd, we’re rolling out this new generation. You know, it continues the kind of leadership in x86 CPUs, but it’s designed in such a way that it matches what I just described a moment ago. It’s optimised for standalone x86 traditional workloads.”
AMD has previously said these Epyc Venice CPUs pack up to 256 Zen 6 cores, marking a 33% core-count increase over current 192-core Epyc Turin chips. These will be the first high-performance computing processors to be produced using TSMC’s 2nm node, with AMD claiming they will offer a 70% boost in CPU performance over Zen 5-based chips. Initially, production will take place at TSMC’s Taiwan facilities, but future manufacturing of these cutting-edge chips will also take place at TSMC’s Arizona fab.
Epyc Venice is expected to debut on AMD’s rumoured new SP7 socket, with early machines at Computex appearing to show PCIe 6.0 support and 16-channel memory. For comparison, the Epyc Turin SP5 platform tops out at 12 memory channels and PCIe 5.0 support
While these capabilities are unlikely to reach consumer desktop platforms anytime soon, the upcoming official reveal may at least give us a glimpse at the gains we can expect in terms of instructions per clock (IPC). For a proper announcement of desktop Zen 6, we may well have to wait until CES 2027 in January.
